1. Field of the Invention
The present invention relates to an interrupt controller that processes external interrupt signals, and more particularly, to a multistage interrupt controller that uses a multistage storage means to process the external interrupt signals.
2. Background of the Related Art
FIG. 1 illustrates a related art single stage interrupt controller. The related art single stage interrupt controller includes a plurality of interrupt reception registers 1, 2, 3 that receive and temporarily store a plurality of external interrupt signals EXTINT0, EXTINT1, EXTINT2, respectively. An interrupt priority determining circuit 4 receives the delayed external interrupt signals IFR0, IFR1, IFR2 from the interrupt reception registers 1, 2, 3, respectively, determines priorities and processes the delayed external interrupt signals IFR0, IFR1, IFR2. A corresponding plurality of accept signals AcceptINT0, AcceptINT1, AcceptINT2 are then generated and transmitted to the respective interrupt reception registers 1, 2, 3, to indicate final interrupt execution.
The interrupt reception registers 1, 2, 3 each include a first AND gate 5 that subjects the external interrupt signal (e.g., EXTINT0) and the inverted accept signal (e.g., AcceptINT0) to a logical AND operation. Each of the interrupt registers 1, 2, 3 also includes a second AND gate 6 that subjects in external clock signal CLK and an inverted feedback signal to a logical AND operation, and a D-flip-flop 7 that delays a signal from the first AND gate 5 for a given time period in accordance with the external clock signal CLK from the second AND gate 6.
The D-flip-flop 7 provides the delayed external interrupt signal (e.g., IFR0) both to the interrupt priority determining circuit 4 and to the second AND gate 6 as the feedback signal. The D-flip-flop 7 can be reset in response to an external reset signal RESET.
The related art single stage interrupt controller receives the external interrupt signals EXTINT0, EXTINT1, EXTINT2, the clock signal CLK, the reset signal RESET, and the accept signals AcceptINT0, AcceptINT1, AcceptINT2 indicating that an interrupt has been executed at the interrupt reception registers 1, 2, 3. Accordingly, the external interrupt signals EXTINT0, EXTINT1, EXTINT2 are synchronized with the clock signal CLK and transmitted to the interrupt priority determining circuit 4 through the interrupt reception registers 1, 2, 3. The interrupt priority determining circuit 4 then generates interrupt signals according to the priority of the delayed external interrupt signals IFR0, IFR1, IFR2.
Upon generation and transmission of the interrupt signal from the interrupt priority determining circuit 4, a device that receives the interrupt signal transits the accept signal AcceptINT0, AcceptINT1, or AcceptINT2 to a xe2x80x9chighxe2x80x9d position. Once the accept signal is transited to the xe2x80x9chighxe2x80x9d position, the first AND gate 5 in each of the interrupt reception registers 1, 2,3 generates a xe2x80x9clowxe2x80x9d signal. The D-flip-flop 7 accordingly generates a xe2x80x9clowxe2x80x9d delayed external interrupt signal (e.g., IFR0) output to the interrupt priority determining circuit 4, and no external interrupt signal (e.g., EXTINT0) is received at the interrupt priority determining circuit 4. Table 1 shows the cyclic operation of the related art single stage interrupt controller.
If the external interrupt signals EXTINT0, EXTINT1, EXTINT2 are received at a logic level of xe2x80x9c1xe2x80x9d, each of the interrupt reception registers 1, 2, 3 generates an external interrupt signal IFR0, IFR1, IFR2 at a logic level of xe2x80x9c1xe2x80x9d. Further, if the priorities are EXTINT0 greater than EXTINT1 greater than EXTINT2, the interrupt priority determining circuit 4 generates the interrupt signals in the order shown in Table 1. Once the interrupt signal is generated, a corresponding accept signal AcceptINT0, AcceptINT1, AcceptINT2 is transited to a logic level of xe2x80x9c1xe2x80x9d to generate a corresponding delayed external interrupt signal IFR0, IFR1, IFR2 at a logic level of xe2x80x9c0xe2x80x9d.
However, the related art interrupt controller has various problems and disadvantages. Since the related art single stage interrupt controller has interrupt flag registers of only one stage, the interrupt controller cannot issue an interrupt signal in multistage, because the interrupt signal is not received, stored, and processed again but it is disregarded, even if an external interrupt signal is received again when the interrupt flag register is at a logic level of xe2x80x9c1xe2x80x9d. As illustrated in FIG. 2, which illustrates waveforms at different units in the related art interrupt controller, even if the external interrupt signals are duplicated, a subsequent external interrupt signal is disregarded while the delayed external interrupt signal (e.g., IFRO) is at a xe2x80x9chighxe2x80x9d level.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
It is a further object of the present invention to recognize subsequent external interrupt signals.
Another object of the present invention is to provide a multistage interrupt controller that can issue interrupt signals in multistage.
To achieve these and other advantages, the multistage interrupt controller includes a plurality of multistage interrupt reception registers, each receiving and storing a plurality of interrupt signals to generate a priority interrupt signal. The multistage interrupt controller also includes an interrupt priority determining circuit coupled to said plurality of multistage interrupt reception registers for receiving corresponding priority interrupt signals, determining priorities of the priority interrupt signals, and generating an output signal in accordance with the priorities. Further, the multistage interrupt controller includes a feedback circuit that receives the priority interrupt signals from the multistage interruption registers to generate a feedback signal to each of the plurality of multistage interrupt reception registers.
The embodiments of the present invention also include a method for generating an interrupt signal that comprises the steps of sequentially delaying a plurality of interrupt signals in response to a feedback signal and a synchronization signal, generating a corresponding plurality of priority interrupt signals; and prioritizing the priority output signals to generate a prioritized interrupt signal.
The embodiments of the present invention further include a multistage interruption register, comprising a plurality of stages coupled in series, wherein each stage receives a feedback signal, and at least one of an interrupt signal and at least one delayed interrupt signal, and a last stage of the plurality of stages generates a priority interrupt signal, and a feedback circuit responsive to the priority interrupt signal generates the feedback signal.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.